1. Field of the Invention
This invention is related to the field of digital systems and, more particularly, to address translation mechanisms in such systems.
2. Description of the Related Art
Address translation is often used in systems that include multiple memory request sources and a memory shared by the sources. The sources can include processors, direct memory access (DMA) units acting on behalf of various peripheral devices, and/or the peripheral devices themselves. Address translation may be used to ensure that different sources do not interfere with each other's access to memory, to provide a larger virtual memory than is actually available in the physical memory (along with software to page data in and out of the memory as needed), etc. Thus, a given source may transmit a memory request with a virtual address, and the address translation mechanism may translate the address to a corresponding physical address.
Typically, the virtual to physical address translations are stored in a set of software-managed page tables in memory. The virtual address can be used as an index (relative to a base address of the page table) from which a page table entry or entries is read in order to locate the correct translation. Some address translation schemes use multiple page table reads in a hierarchical or non-hierarchical fashion to locate a translation. Other schemes can use a single page table read to locate a translation.
The latency for performing the translation can be reduced by providing a translation lookaside buffer (TLB) that caches recently used translations for rapid access in response to a memory request from a source. The TLB is a finite resource, and can be shared by multiple requesters. Thus, the TLB is subject to potential interference by different sources (e.g. different sources, using different translations, can dislodge recently used translations corresponding to other sources). The competition for TLB space can reduce overall performance by increasing the latency for memory requests among the sources that are competing because of the increase in TLB misses.